1. Field of the Invention
The present invention relates to a memory module, and more particularly to a memory module that includes a data register buffer for buffering read data read from memory devices and write data to be written to the memory devices.
2. Description of Related Art
Memory modules such as a dual inline memory module (DIMM) are configured so that a large number of memory chips such as dynamic random access memories (DRAMs) are mounted on a module substrate. Such a memory module is inserted into a memory slot arranged on a motherboard, whereby data transfer between the memory module and a memory controller is performed. Memory capacities that are required by the system have been extremely large in recent years, and it is difficult for a single memory module to provide a needed memory capacity. Most motherboards have a plurality of memory slots so that a plurality of memory modules can be mounted.
If a plurality of memory modules are mounted on the motherboard, the load capacitance of the data wiring on the motherboard increases to deteriorate signal quality. Such a problem is not significant when the data transfer rate between the memory controller and the memory modules is rather low. If the data transfer rate between the memory controller and the memory modules is high, a problem occurs because proper data transfer fails due to deterioration of signal quality.
Memory modules called load reduced memory modules are known to be capable of reducing the load capacitance of the data wiring (see Japanese Patent Application Laid-Open No. 2010-282510). The load reduced memory module described in Japanese Patent Application Laid-Open No. 2010-282510 includes a plurality of data register buffers. The data register buffers function to buffer write data supplied from a memory controller and supply the write data to a plurality of memory chips, and buffer read data supplied from a plurality of memory chips and supply the read data to the memory controller.
In the memory module described in Japanese Patent Application Laid-Open No. 2010-282510, the plurality of data register buffers are arranged near connectors. The wiring distances from the memory chips mounted on a memory mounting area closer to the connectors to the data register buffers are therefore different from those from the memory chips mounted on a memory mounting area farther from the connectors to the data register buffers. As a result, data skew occurs between the memory chips mounted on the memory mounting area closer to the connectors and the memory chips mounted on the memory mounting area farther from the connectors.